MELSEC-Q Series QCPU Modules

The MELSEC Q Series

Automation Platform

Q Series stands apart from conventional PLCs. It is a new, multidisciplinary automation platform addressing needs of OEMs and end users scalable across the general scope of automation applications from smaller to very large systems. While PLCs are typically limited to sequence control, Q Series offers a broad spectrum of different automation capabilities. We refer to it as an “automation platform”, as sequence control is just one of its many capabilities. It is equally capable of process, sophisticated motion and open, PC based control, either individually, or simultaneously. Hence Q Series is much more than just a PLC.

Features Include:

  • Spans a range of CPU types from small/medium systems, to complex networked systems handling tens of thousands of I/O, addressing the needs of all applications.    
  • Embraces contemporary technologies such as high speed Ethernet, open systems and Internet capabilities, to reduce lifecycle costs via remote system management & maintenance.
  • Increases productivity throughout a system life cycle of design, implementation and maintenance by offering a range of capabilities that allow more to be achieved in less time.
  • Multiple CPU capability adds open ended system performance and flexibility.
  • Multiple program capability allows concurrent development, code reuse, better program organization and faster troubleshooting for less downtime.
  • Multiple access to the system allows many technicians to work simultaneously for faster system debugging and maintenance.
  • High productivity GX Developer programming tools permit designers to concentrate on the automation of their system, not the configuration of the controller.           
  • Networking & communication options distribute Q Series systems over wide areas while reducing wiring costs.          
  • Sequence CPUs can also address process applications by means of built-in PID capabilities.
  • Extremely compact package saves panel costs.
  • Certified by UL, cUL, CE as indicated and DNV, ABS, BV, RINA, LR & NK shipping approvals for all Q Series.
  • Redundant CPU capability available for hot-backup of critical systems.

 

Basic Model Sequence CPUs

These CPUs offer an economical entry-level version of the Q Series for small scale systems. 

Special Features:

  • Multiple CPU supportt; use up to three CPUs to combine sequence, motion & PC control on a single system (Version B or later)
  • Compatibility with Q Series Intelligent Function Utility configuration tools              
  • Offers full range of Q Series network & communication features, including 100Mbit Ethernet, Internet functions & NET/H              
  • Integrated PSU, CPU and 5 slot unit available to simplify system construction 
    (Q00JCPU-E)             
  • Built in serial communications via CPU port (using MELSEC Communication (MC) protocol)              
  • Security functions     
  • Flash memory for programs & parameters
  • Supports floating point, fuction block, PID and SFC programming (Version B or later)


Required Manuals

Model Number

Description

Contents

Included with CPU?

Stocked Item

IB(NA)0800061

QCPU(Q mode) CPU Module
User’s Manual (Hardware)

General specs, CE compliance information, Installation, Safety requirements, Power supply wiring, Overview of system parts

No (included with base units)

SH(NA)080483ENG

Q CPU (Q Mode) User’s Manual (Hardware Design, Maintenance & Inspection)

CPU H/W specs, PSU spec, Base Unit specs, CE compliance information, Maintenance & inspection, Installation, Troubleshooting

No (purchase separately)

S

SH(NA)080484ENG

QCPU(Q Mode) User’s Manual (Function Explanation, Program Fundamentals)

CPU specifications, system configuration, programming basics, I/O assignments, memory organization, CPU functions, communication with intelligent function modules, parameters & devices, program up/downloads, overview of multiple program architecture, programming basics, overview of multiple CPU system

No (purchase separately)

S

SH(NA)080485ENG

QCPU User’s Manual
(Multiple CPU System)

Outline, system configuration, concept for multiple CPU system, communication between CPU modules, processing time of QCPU in multiple CPU system, parameter added for multiple CPU system, precautions for use of AnS Series module, starting up the multiple CPU system

No (purchase separately)

S

SH(NA)080039

QCPU(Q Mode)/QnACPU Programming Manual
(Common Instructions)

General Description, Instruction Tables, Configuration of Instructions, How To Read Instructions, Sequence Instructions, Basic Instructions, Application Instructions, Instructions For Data Link, QCPU Instructions, Redundant System Instructions, Error Codes

No (purchase separately)

SH(NA)080041

QCPU(Q Mode)/QnACPU Programming Manual (SFC)

General Description, System Configuration, Specifications, SFC Program Configuration, SFC Program Processing Sequence, SFC Program Execution

No (purchase separately)

SH(NA)080076

Q CPU (Q Mode) Programming Manual (MELSAP-L)

General Description, System Configuration, Specifications, SFC Program Configuration, SFC Program Processing Sequence, SFC Program Execution

No (purchase separately)

SH(NA)080040

QCPU(Q Mode)/QnACPU Programming Manual
(PID Control Instructions)

General Description, System Configuration for PID Control, PID Control Specifications, Functions of PID Control, PID Control Procedure, PID Control Instructions, How To Read Explanations For Instructions, Incomplete Derivative PID Control Instructions and Program Examples, Complete Derivative PID Control Instructions and Program Examples

No (purchase separately)

SH(NA)080368

Programming Guide Book for Structured Text (ST)

Covers Structured Text programming method

No (purchase separately)

Note: Many of these manuals are available by free download from our website, www.sysprotex.com
Note: Version B multiple CPU features do not apply to Q00JCPU-E.

 

Basic Model CPU

Model Number

Q00JCPU-E

Q00JCPU-S8

Q00CPU

Q01CPU

Stocked Item

S

S

S

S

Certification

UL • cUL • CE

UL • cUL • CE

UL • cUL • CE

UL • cUL • CE

Hardware Format

Combined CPU, PSU and
5-Slot Base Unit

Combined CPU, PSU and
8 slot Base Unit

Stand alone CPU

Stand alone CPU

Control Method

Repeated operation using stored program

I/O Control Method

Refresh mode

Programming Language (Sequence Control Dedicated Language)

Relay symbol type (ladder) logic symbolic language (list)

Processing Speed (Sequence Instruct)

LD X0

200ns

160ns

100ns

MOV
(MOV D0 D1)

700ns

560ns

350ns

Total Number of Instructions

249 (excluding intelligent function module dedicated instructions)

Constant Scan (ms) (Program Start at Given Time Intervals)

1 to 2000ms (can be specified in 1ms increments)

Program Capacity (*1)

8k steps (32 kbyte)

8k steps (32 kbyte)

14k steps (56 kbyte)

Memory Capacity

Program Memory
(Drive 0)

58 kbyte

94 kbyte

Standard RAM (Drive 3)

0

64 kbyte

Standard ROM (Drive 4)

58 kbyte

94 kbyte

Number of Stored Programs

Program Memory

1

1

1

1

Standard ROM

1

1

1

1

Number of Stored
File Registers

Standard RAM

1

1

Number of I/O Device Points

2048 points (X/Y0 to 7FF) (*2)

Number of I/O Points

256 points (X/Y0 to FF)

1024 points (X/Y0 to 3FF) (*3)

Internal Relay [M]

Default 8192 points (M0 to 8191)

Latch Relay [L]

2048 points (L0 to 2047)

Link Relay [B]

2048 points (B0 to 7FF)

Timer [T]

Default 512 points (T0 to 511) (used as low-speed or high-speed timer)
Switching between low-speed and high-speed timers is set by instruction
Low-speed/high-speed timer timing increments are parameter-set
(Low-speed timer: 1 to 1000ms, 1ms increments, default 100ms)
(High-speed timer: 0.1 to 100ms, 0.1ms increments, default 10ms)

Retentive Timer [ST]

Default 0 point (ST0 to 511) (used as low-speed or high-speed timer)
Switching between low-speed and high-speed timers is set by instruction
Low-speed/high-speed timer timing increments are parameter-set.
(Low-speed timer: 1 to 1000ms, 1ms increments, default 100ms)
(High-speed timer: 0.1 to 100ms, 0.1ms increments, default 10ms)

Counter [C]

Normal counters Default 512 points (C0 to 511)
Interrupt counters Max. 128 (Default 0 points, parameter setting)

Data Register [D]

Default 11136 points (D0 to 11135)

Link Register [W]

Default 2048 points (W0 to 7FF)

Annunciator [F]

Default 1024 points (F0 to 1023)

Edge Relay [V]

Default 1024 points (V0 to 1023)

File Register

[R]

None

32768 points (R0 to 32767)

[ZR]

None

32768 points (ZR0 to 32767)

Special Link Relay [SB]

1024 points (SB0 to 3FF)

Special Link Register [SW]

1024 points (SW0 to 3FF)

Step Relay (*4)

2048 points (SW0 to 3FF)

Index Register [Z]

10 points (Z0 to 9)

Pointer [P]

300 points (P0 to 299)

Interrupt Pointer [I]

128 points (I0 to 127)
In parameters, set the cyclic intervals of the system interrupt pointers I28 to I31 (2 to 1000ms, 1ms increments)

Special Relay [SM]

1024 points (SM0 to 1023)

Special Register [SD]

1024 points (SD0 to 1023)

Function Input [FX]

16 points (FX0 to F)

Function Output [FY]

16 points (FY0 to F)

Function Register [FD]

5 points (FD0 to 4)

Link Direct Device

Device for direct access to link device.
Dedicated. Specified format: J nn \ nn

Intelligent Function Module Direct Device

Device for direct access to buffer memory of intelligent function module.
Specified format: Unn \G nn

Latch (Power Failure Comp.) Range

L0 to 2047 (default)
(Latch range setting can be made for B, F, V, T, ST, C, W and D)

Remote RUN/PAUSE Contact

1 point can be set for each RUN and PAUSE contacts from X0-7FF.

Clock Function

Year, month, day, hour, minute, second, day of week
(Automatic leap year judgment)
Accuracy –3.2 to +5.27 (TYP +1.98) s/day at 0°C
Accuracy –2.57 to +5.27 (TYP +2.22) s/ day at 25°C
Accuracy –11.68 to +3.65 (TYP –2.64) s/ day at 55°C

Permissible Instantaneous Power Failure Time

20ms

Depends on power supply module

5 VDC Internal Current Consumption (A)

0.22

0.25

0.27

Weight (kg)

0.66

0.13

Dimensions W x H x D mm (in)

245 (9.65) x 98 (3.86) x 98 (3.86)

27.4 (1.08) x 98 (3.86) x 89.3 (3.52)

Notes:
1. Maximum actual program size is (program capacity – 34 steps)
2. Sum of the number of I/O points on the main/extension base directly controlled by the CPU module and the number of I/O points controlled as remote I/O by the remote I/O network.
3. Number of I/O points on the main/extension base directly controlled by the CPU module.
4. The “Step relay” is a device for the SFC fucntion, only applicable to version B CPUs.

 

High Performance Model Sequence CPUs

Features Include:

  • Multiple CPU support; use up to four CPUs to combine sequence, process, motion & PC control on a single system in any combination           
  • Multiple program capability; allows up to 124 separate programs, depending on CPU type           
  • Multiple access to CPUs by several technicians simultaneously           
  • Very broad range of CPU capabilities           
  • Very high speed processing capability           
  • USB connection to CPU for rapid upload/download of programs           
  • Up to 32MB of data storage by use of removable memory cards
  • Supports floating point, PID and SFC programming

Please refer to the configuration diagram at the beginning of the Q Series section for details on configuring a multiple CPU system.



Required Manuals

Model Number

Description

Contents

Included with CPU?

Stocked Item

IB(NA)0800061

QCPU(Q mode) CPU Module
User’s Manual (Hardware)

General specs, CE compliance information, Installation,
Safety requirements, Power supply wiring, Overview of system parts

No
(included with base units)

SH(NA)080483ENG

QCPU (Q Mode) User’s Manual
(Hardware Design, Maintenance & Inspection)

CPU H/W specs, PSU specs, Base Unit specs, Memory Card specs, CE compliance information, Installation, Maintenance & inspection, Troubleshooting

No
(purchase separately)

S

SH(NA)080484ENG

QCPU(Q Mode) User’s Manual
(Function Explanation, Program Fundamentals)

CPU specifications, System configuration, Programming basics,
I/O assignments, Memory organization, CPU functions,
Communication with intelligent function modules, Parameters & devices, Program up/downloads, Overview of multiple program architecture, Programming basics

No
(purchase separately)

S

SH(NA)080485ENG

QCPU User’s Manual (Multiple CPU System)

Outline, system configuration, concept for multiple CPU system,
communication between CPU modules, processing time of QCPU in multiple CPU system, parameter added for multiple CPU system, precautions for use of AnS Series module, starting up the multiple CPU system

No
(purchase separately)

S

SH(NA)080039

QCPU(Q Mode)/QnACPU Programming Manual (Common Instructions)

General Description, Instruction Tables, Configuration of Instructions, How To Read Instructions, Sequence Instructions, Basic Instructions, Application Instructions, Instructions For Data Link, QCPU Instructions, Redundant System Instructions, Error Codes

No
(purchase separately)

SH(NA)080041

QCPU(Q Mode)/QnACPU Programming Manual (SFC)

General Description, System Configuration, Specifications,
SFC Program Configuration, SFC Program Processing Sequence,
SFC Program Execution

No
(purchase separately)

SH(NA)080076

Q CPU (Q Mode) Programming Manual (MELSAP-L)

General Description, System Configuration, Specifications,
SFC Program Configuration, SFC Program Processing Sequence,
SFC Program Execution

No
(purchase separately)

SH(NA)080040

QCPU(Q Mode)/QnACPU Programming Manual (PID Control Instructions)

General Description, System Configuration for PID Control, PID Control Specifications, Functions of PID Control, PID Control Procedure, PID Control Instructions, How To Read Explanations For Instructions, Incomplete Derivative PID Control Instructions and Program Examples, Complete Derivative PID Control Instructions and Program Examples

No
(purchase separately)

SH(NA)080368

Programming Guide Book for
Structured Text (ST)

Covers Structured Text programming method

No
(purchase separately)



High Performance Model CPUs

Item

Q02CPU

Q02HCPU

Q06HCPU

Q12HCPU

Q25HCPU

Stocked Item

S

S

S

S

S

Certification

UL• cUL • CE

UL • cUL • CE

UL • cUL • CE

UL • cUL • CE

UL • cUL • CE

Control System

Repeated operation using stored program

I/O Control Method

Refresh mode

Programming Language

Language dedicated to sequence control
Relay symbol type (ladder), logic symbolic language

Processing Speed

LD (LD X10)

79ns

34ns

(Sequence Instruc.)

MOV (MOV D0 D1)

237ns

102ns

Total Number of Instructions

360 (excluding intelligent function module dedicated instructions)

Constant Scan (Program Start at Given Time Intervals)

0.5 to 2000ms (can be specified in 0.5ms increments)

Program
Capacity *

Program Memory
(Drive 0)

28k steps

28k steps

60k steps

124k steps

252k steps

Memory Capacity

Memory Card (RAM)
(Drive 1)

Capacity of loading memory cards (2 Mbyte max.)

Memory Card (ROM)
(Drive 2)

Installed memory card capacity (Flash card: 4 Mbyte max., ATA card: 32 Mbyte max.)

Standard RAM
(Drive 3)

64 kbyte

128 kbyte

128 kbyte

256 kbyte

256 kbyte

Standard ROM
(Drive 4)

112 kbyte

112 kbyte

240 kbyte

496 kbyte

1008 kbyte

CPU Shared
Memory

8 kbyte (not latched)

Maximum Number
Of Stored Files

Program Memory

28

28

60

124

252 (*2)

Memory Card (RAM)

256

Memory
Card (ROM)

Flash

288

ATA

512

Standard RAM

2

Standard ROM

28

28

60

124

252 (*2)

Standard ROM Number of Writings

Max. 100,000 times

Number of I/O Device Points

8192 points (X/Y0 to 1FFF) (*3)

Number of I/O Points

4096 points (X/Y0 to FFF) (*4)

Number of
Device Points

Internal Relay [M]

Default 8192 points (M0 to 8191)

Latch Relay [L]

Default 8192 points (L0 to 8191)

Link Relay [B]

Default 8192 points (B0 to 1FFF)

Timer [T]

Default 2048 points (T0 to 2047) (used as low-speed or high-speed timer)
Switching between low-speed and high-speed timers is set by instruction
Low-speed/high-speed timer timing increments are parameter-set
(Low-speed timer: 1 to 1000ms, 1ms increments, default 100ms)
(High-speed timer: 0.1 to 100ms, 0.1ms increments, default 10ms)

Retentive Timer [ST]

Default 0 (ST0 to 2047) (used as low-speed or high-speed timer)
Switching between low-speed and high-speed timers is set by instruction
Low-speed/high-speed timer timing increments are parameter-set
(Low-speed timer: 1 to 1000ms, 1ms increments, default 100ms)
(High-speed timer: 0.1 to 100ms, 0.1ms increments, default 10ms)

Counter [C]

Normal counters Default 1024 points (C0 to 1023)
Interrupt counters Max. 2128 points. (Default 0 points, parameter setting)

Data Register [D]

Default 12288 points (D0 to 12287)

Link Register [W]

Default 8192 points (W0 to 1FFF)

Annunciator [F]

Default 2048 points (F0 to 2047)

Edge Relay [V]

Default 2048 points (V0 to 2047)

File Register [R]

When standard RAM is used:
Q02CPU: 32768 points (R0 to 32767)
Q02HCPU, Q06HCPU: The number of points of up to 65536 points can be used by block conversion in increments of 32768 points (R0 to 32767)
Q12HCPU, Q25HCPU: The number of points of up to 131072 points can be used by block conversion in increments of 32768 points (R0 to 32767)
• When a SRAM card (1 Mbyte) is used: The number of points of up to 517120 points can be used by block conversion increments of 32768 points (R0 to 32767)
• When a SRAM card (2 Mbyte) is used: The number of points up to 1041408 points can be used by block conversion increments of 32768 points (R0 to 32767)
• When a Flash card (2 Mbyte) is used: The number of points up to 1041408 points can be used by block conversion increments of 32768 points (R0 to 32767)
• When a Flash card (4 Mbyte) is used: The number of points up to 1042432 points can be used by block conversion increments of 32768 points (R0 to 32767)

File Register [ZR]

When standard RAM is used:
Q02CPU: 32768 points (ZR0 to 32767)
Q02HCPU, Q06HCPU: 65536 points (ZR0 to 65535), No block conversion necessary
Q12HCPU, Q25HCPU: 131072 points (ZR0 to 131071), No block conversion necessary
• When a SRAM card (1 Mbyte) is used: 517120 points (ZR0 to 517119), No block conversion necessary
• When a SRAM card (2 Mbyte) is used: 1041408 points (ZR0 to 1041407), No block conversion necessary
• When a Flash card (2 Mbyte) is used: 1041408 points (ZR0 to 1041407), No block conversion necessary
• When a Flash card (4 Mbyte) is used: 1042432 points (ZR0 to 1042431), No block conversion necessary

Note: 124 is the maximum number of programs that can be executed on High Performance model QCPU.

 

High Performance Model Sequence CPUs (continued)

Item

Q02CPU

Q02HCPU

Q06HCPU

Q12HCPU

Q25HCPU

Number
of Device
Points

Special Link Relay [SB]

[SB] 2048 points (SB0 to 7FF)

Special Link Register [SW]

[SW] 2048 points (SW0 to 7FF)

Step Relay [S]

8192 points (S0 to 8191)

Index Register [Z]

16 points (Z0 to 15)

Pointer [P]

4096 points (P0 to 4095), set in parameters the range in which the pointers/common
pointers are used

Interrupt Pointer [I]

256 points (I0 to 255)
In parameters, set the cyclic intervals of the system interrupt pointers I28 to I31
(0.5 to 1000ms, 0.5ms increments)

Special Relay [SM]

2048 points (SM0 to 2047)

Special Register [SD]

2048 points (SD0 to 2047)

Function Input [FX]

16 points (FX0 to F)

Function Output [FY]

16 points (FY0 to F)

Function Register [FD]

5 points (FD0 to 4)

Link Direct Device

Device for direct access to link device. Specified format: J_ _  \ _ _

Intelligent Function Module Direct Device

Device for direct access to buffer memory of intelligent function module.
Specified format:_ _  \ G_ _

Latch (Power Failure Comp.) Range

L0 to 8191 (default) (Latch range setting can be made for B, F, V, T, ST, C, W and D)

Remote RUN/PAUSE Contact

1 point can be set for each RUN and PAUSE contacts from X0-1FFF

Clock Function

Year, month, day, hour, minute, second, day of week (Automatic leap year judgment)
Accuracy –3.18 to +5.25 (TYP +2.12) s/d @ 0°C; Accuracy –3.93 to +5.25 (TYP +1.90) s/d @ 25°CAccuracy –14.69 to +3.53 (TYP –3.67) s/d @ 55°C

Permissible Instantaneous Power Failure Time

Depends on power supply module

5 VDC Internal Current Consumption (A)

0.60

0.64

0.64

0.64

0.64

Weight (kg)

0.20

0.20

0.20

0.20

0.20

Dimensions (W x H x D) mm (in)

27.4 (1.08) x 98 (3.86) x 89.3 (3.52)


Notes:
1. Maximum program size is (program size – 34 steps)
2. Maximum number of programs is 124.
3. Sum of the number of I/O points on the main/extension base directly controlled by the CPU module and the number of I/O points controlled as remote I/O by the remote I/O network.
4. Number of I/O points on the main/extension base directly controlled by the CPU module.


Motion CPUs

Q Series motion CPUs offer the ability to integrate complex motion systems on a Q Series system alongside sequence, process & PC based functions. The motion CPUs allow costly, inflexible mechanical systems to be replaced by multiple axis motion control that is significantly easier and less expensive to design, build and re-configure. 

Key Features

  • Up to 32 axes controlled by one CPU, allowing up to 96 axes per base rack         
  • Servo axes connect quickly and easily via daisy chain connection on SSCNET, eliminating complex, expensive wiring harnesses         
  • SSCNET offers high speed, deterministic control of each axis independently         
  • Allows integration with other automation technologies such as open language program control and Ethernet/Internet capabilities

 

Manual

Model Number

Description

Contents

Included with CPU?

Stocked Item

IB(NA)0300040

Q172CPU(N)/Q173CPU(N) User’s Manual

Covers the Q172CPUN and Q173CPUN

No (purchase separately)

S

 

Motion CPUs

Item

Q173CPUN

Q172CPUN

Stocked Item

S

S

Certification

UL • cUL • CE

UL • cUL • CE

Number of Control Axes

32 axes

8 axes

Operation Cycle

Approx. 0.88ms

Interpolation Function

Linear interpolation (Max.4-axes), Circular interpolation (2-axes),
helical interpolation (3-axes)

Control Method

PTP (Point to Point), speed control, speed-position control, fixed-pitch feed, constant-speed control, position follow-up control, speed-switching control high speed oscillation control, synchronous control

Acceleration/Deceleration Process

Automatic trapezoidal acceleration/deceleration,
S-curve acceleration/deceleration

Compensation Function

Backlash compensation, Electronic gear

Program Language

Motion SFC, Dedicated instructions, Mechanical support language

Program Capacity

14K steps

Number of Positioning Points

3,200 points (Positioning data can be designated indirectly)

Zeroing Function

Proximity dog type, Count type, Data setting type

JOG Operation Function

Available

Sync. Encoder Operation Function

12 units can be connected

8 units can be connected

M-Function

M-code output function, M-code completion wait function

Absolute Position System

Available by adding a battery to Servo Amplifier
(Absolute or incremental system can be specified per axis)

SSCNET I/F

5CH

2CH

Number of Modules Connected

Max. 64 modules (Number of Q-series Extension Base: Max.7)

Pulse Generator

Q172PX  4 modules can be used per CPU

Q172PX  1 module can be used per CPU

Synchronous Encoder,
Servo

Q172EX  6 modules can be used per CPU

Q172EX  4 modules can be used per CPU

External Signal Input Module

Q173LX  4 modules can be used per CPU

Q173LX  3 modules can be used per CPU

Weight (kg)

0.25

0.25

Dimensions (W x H x D) mm (in)

27.4 (1.08) x 98 (3.86) x 114.3 (4.50)

27.4 (1.08) x 98 (3.86) x 114.3 (4.50)




Motion CPUs

Item

Q173CPUN • Q172CPUN

Stocked Item

S

Certification

UL, cUL, CE

Program
Capacity

Code Total (Motion SFC Chart + Operation Control + Transition)

287K bytes

Text Total (Operation Control + Transition)

224K bytes

SFC
Program

Number of Motion SFC Program

256 (No. 0 to 255)

Motion SFC Chart Size / Program

Max. 64K bytes (included Motion 
SFC chart comments)

Motion SFC Steps / Program

Max. 4094 steps

Number of Selective Branch / Branch

255

Number of Parallel Branch / Branch

255

Nesting of Parallel Branch

Max. 4 levels

 

Operation
Control 
Program (F/FS),
Transition
Program (G)

Number of Operation Control Programs

4096 with F (Once execution type) and
FS (Scan execution type) combined (F/FS0 to F/FS4095)

Number of Transition Programs

4096 (G0 to G4095)

Code-Size/Program

Max. approx. 64k bytes (32766 steps)

Number of Blocks (Lines) / Program

Max. 8192 blocks (in the case of 4 steps (min)/block)

Number of Characters / Block (Line)

Max. 128 characters (comment included)

Number of Operand / Block (Line)

Max. 64 (operand: constants, word devices, bit devices)

Nesting of ( ) / Block

Max. 32 levels

Descriptive
Expression

Operation Control Program

Calculation expression/ bit conditional expression/

Transition Program

comparison conditional expression

Executed
Specification

Number of Multi Executed Programs

Max. 256 programs

Number of Multi Active Steps

Max. 256 steps/all programs

Executed
Task

Normal Task

Executed in motion main cycle

Event Task
(Available Mask)

Fixed Cycle

Fixed cycle (0.88ms, 1.77ms, 3.55ms, 7.11ms, 14.2ms)

External Interrupt

Execute it when setted input is ON in 16 input point of QI60 external interrupt module

PLC Interrupt

Execute with interrupt from PLC

 

NMI Task

Execute it when setted input is ON in 16 input point of QI60 external interrupt module

Number of Input / Output (X/Y)

8192 points

Number of Actual Input / Output (PX/PY)

256 points

Device

Internal Relay (M)

Total 8192 points

Latch Relay (L)

Total 8192 points

Link Relay (B)

8192 points

Annunciator (F)

2048 points

Special Relay (M)

256 points

Data Register (D)

8192 points

Link Register (W)

8192 points

Special Register (D)

256 points

Motion Device (#)

8192 points

Free Run Timer (FT)

1 point (888 micro second)



 

Process Control CPUs

These CPUs include a wide variety of process control functions so that they are optimized to the task of controlling large scale, complex continuous processes. This allows a Q Series system to fully address the needs of users outside of the scope of traditional discrete control applications.

Key features:

  • 52 process control instructions added to standard instruction set        
  • Floating point math coprocessor dedicated to float ing point and process control operations
  • Autotunig PID with 2 degrees of freedowm (responds to both set value and disturbance)   
  • Compensation functions to allow loop modeling closer to the actual process        
  • Process alarm functions related to high, low and deviation process and manipulated variable values        
  • Tracking functions to allow bump less transfer between manual and automated control
  • Hot swappable

 

Required Manuals

Model Number

Description

Contents

Included with CPU?

Stocked Item

IB(NA)0800061

QCPU (Q mode) CPU Module User’s Manual (Hardware)

General specs, CE compliance information, installation, safety requirements, power supply wiring, overview of system parts

No (included with base units)

SH(NA)080039

QCPU (Q Mode)/QnACPU Programming Manual

Covers all basic and applied instructions for both the Q and QnA CPU families, key resource for programming

No (purchase separately)

SH(NA)080041

QCPU (Q Mode)/QnACPU Programming Manual (SFC)

Covers sequential function chart, (SFC) programming, Programming Manual (SFC), A graphical, flowchart style alternative to ladder logic programming

No (purchase separately)

SH(NA)080040

QCPU (Q Mode)/QnACPU Programming Manual (PID Control Instructions)

Covers Proportional, Integral, Derivative (PID) programming for process control applications

No (purchase separately)

SH(NA)080483ENG

Q CPU (Hardware Design, Maintenance and Inspection) User’s Manual

Overview, system configuration, general specifications, power supply units, base unit & extension cables, memory card & battery, EMC & low voltage directive, loading & installation, maintenance & inspection, troubleshooting

No (purchase separately)

S

SH(NA)080484ENG

Q CPU (Function Explanation, Program Fundamentals) User’s Manual

Overview, system configuration, performance specification, sequence program configuration & execution conditions, assignment of I/O numbers, process CPU files, function, comms. with intelligent function modules, parameter list, devices, process CPU processing time, procedure for writing programs to process CPU, outline of multiple CPU systems, system configuration of MCS, allocating MCS I/O nos. comms. Between CPU modules in MCS, comms. between MCS I/O and IFM, processing time for MCS, starting up MCS

No (purchase separately)

S

SH(NA)080485ENG

QCPU User’s Manual (Multiple CPU System)

Outline, system configuration, concept for multiple CPU system, communication between CPU modules, processing time of QCPU in multiple CPU system, parameter added for multiple CPU system, precautions for use of AnS Series module, starting up the multiple CPU system

No (purchase separately)

S

SH(NA)080316

QnPHCPU/QnPRHCPU (Process Control Instructions) Programming Manual

Overview, structure & combinations of process control, instructions, data used for process control instructions, how to execute PCI, execution condition switching & functions, instruction list, how to read instruction list, I/O control instructions, control operator instructions, compensation operator instructions, arithmetic operation instructions, comparison operation instructions, auto tuning, error codes, appendices

No (purchase separately)

SH(NA)080368

Programming Guide Book for Structured Text (ST)

Covers Structured Text programming method

No (purchase separately)


Process Control CPUs

Item

Q12PHCPU

Q25PHCPU

Stocked Item

S

S

Control Method

Repetitive operation of stored program

I/O Control Mode

Refresh mode. Direct I/O is possible by direct I/O specification (DX_, DY_)

Programming Language (Sequence Control Dedicated Language)

Relay symbol language, logic symbolic language, MELSAP3 (SFC), MELSAP-L, Function block

Processing Speed
(Sequence Instruction)

LD X0

0.034 µs

MOV D0 D1

0.102 µs

Total Number of Instructions

415 (excluding intelligent function module dedicated instructions)

Constant Scan (ms) (Function for Setting the Scan Timer to Fixed Settings)

0.5 to 2000 (Configurable in increments of 0.5 ms). Set parameter values to specify

Program Capacity (*1)

Program Memory (Drive 0)

124k step

252k step

Memory
Capacity

Memory Card (RAM) Drive 1

Capacity of loading memory cards (2Mbyte max.)

Memory Card (ROM) Drive 2

Installed memory card capacity (Flash card: 4 Mbyte max., ATA card: 32 Mbyte max.)

Standard RAM Drive 3

256 kbyte

Standard ROM Drive 4

496 kbyte

1008 kbyte

CPU Shared Memory

8 kbyte (not latched)

Maximum Number of Stored Files

Program Memory

124

252 (*2)

Memory Card (RAM)

256

Memory Card (ROM)

Flash Card

288

ATA Card

512

Standard RAM

2 (only one file register and one local device)

Standard ROM

124

252

Standard ROM Number of Write Cycles

Max. 100,000 times

Number of I/O Device Points

8192 points (X/Y0 to 1 FFF) (Number of devices usable in program)

Number of Occupied I/O Points

4096 points (X/Y0 to FFF) Number of points accessible to actual I/O modules

Number of Device Points

Internal Relay [M]

Default 8192 points (M0 to 8191)

Latch Relay [L]

Default 8192 points (L0 to 8191)

Link Relay

Default 8192 points (B0 to 1FFF)

Timer [T]

Default 2048 points (T0 to 2047) (for low/high speed timer) Select between low / high speed timer by instructions
The measurement unit of the low / high speed timer is set with parameters.
Low speed timer: 1 to 1000ms, 1 ms/unit, default 100ms
High speed timer: 0.1 to 100ms, 0.1ms/unit, default 10ms

Retentive Timer [ST]

Default 0 points for low/high speed retentive timer. Switchover between the low/high speed retentive timer is set by instructions. The measurement unit of the low/high speed retentive timer is set with parameters
Low speed retentive timer: 1 to 1000ms, 1 ms/unit, default 100ms
High speed retentive timer: 0.1 to 100ms, 0.1ms/unit, default 10ms

Counter [C]

Normal counter default 1024 points (C0 to 1023)
Interrupt counter maximum 256 points (default 0 point, set with parameters)

Data Register [D]

Default 12288 points (D0 to 12287)

Link Register [W]

Default 8192 points (W0 to 1FFF)

Annunciator [F]

Default 2048 points (F0 to 2047)

Edge Relay [V]

Default 2048 points (V0 to 2047)

File Register

[R]

When a standard RAM is used: The number of points of up to 131072 points can be used by block conversion in increments of 32768 points (R0 to 32767)
When a SRAM card (1 Mbyte) is used: The number of points of up to 517120 points can be used by block conversion increments of 32768 points (R0 to 32767)
When a SRAM card (2 Mbyte) is used: The number of points up to 1041408 points can be used by block conversion increments of 32768 points (R0 to 32767)
When a Flash card (2 Mbyte) is used: The number of points up to 1041408 points can be used by block conversion increments of 32768 points (R0 to 32767)
When a Flash card (4 Mbyte) is used: The number of points up to 1042432 points can be used by block conversion increments of 32768 points (R0 to 32767)

[ZR]

When a standard RAM is used: 131071 points (ZR0 to 517119), No block conversion necessary
When a SRAM card (1 Mbyte) is used: 517120 points (ZR0 to 517119), No block conversion necessary
When a SRAM card (2 Mbyte) is used: 1041408 points (ZR0 to 1041407), No block conversion necessary
When a Flash card (2 Mbyte) is used: 1041408 points (ZR0 to 1041407), No block conversion necessary
When a Flash card (4 Mbyte) is used: 1042432 points (ZR0 to 1042431), No block conversion necessary

Special Link Relay [SB]

2048 points (SB0 to 7FF)

Special Link Register [SW]

2048 points (SW0 to 7FF)

Step Relay [S]

8192 points (S0 to8191)

Index Register [Z]

16 points (Z0 to 15)

Pointer [P]

4096 points (P0 to 4095) set parameter values to select usable range of in-file pointer/ shared pointers

Interrupt Pointer [I]

256 points (I0 to 255)
The specified intervals of the system interrupt pointers I28 to I31 can be set with parameters. (0.5 to 1000ms, 0.5ms/unit)
Default I28: 100ms; I29: 40ms; I30: 20ms; I31: 10ms

Special Relay [SM]

2048 points (SM0 to 2047)

Special Register [SD]

2048 points (SD0 to 2047)

Function Input [FX]

16 points (FX0 to F)

Function Output [FY]

16 points (FY0 to F)

Function Register [FD]

5 points (FD0 to 4)

Link Direct Device

Device having a direct access to link device. MELSECNET/10(H) use only
Specified form: J_ _ \X_ _, J_ _ \Y_ _, J_ _ \W_ _, J_ _ \B_ _, J_ _ \SW_ _, J_ _ \SB_ _

Intelligent Function Module Device

Device having a direct access to the buffer memory of the intelligent function module,
Specified form U_ _ \G_ _

Latch (Power Failure Compensation) Range

L0 to 8191 (default) (Latch range can be set for B, F, V, T, ST, C, D, and W)

Remote RUN/PAUSE Contact

RUN and PAUSE contacts can be set from among X0 to 1FFF, respectively

Clock Function

Year, month, day, hour, minute, second, day of the week (leap year automatic distinction)
Accuracy -3.18 to +5.25s (TYP. +2.12s)/d at 0°C; Accuracy -3.93 to +5.25s (TYP. +1.90s)/d at 25°C;
Accuracy -14.69 to +3.53s (TYP. -3.67s)/d at 55°C;

Allowable Momentary Power Failure Period

Varies according to the type of power supply module

5 VDC Internal Current Consumption

0.64A

Weight

0.20 kg

Dimensions (W x H x D) mm (in)

98 (3.86) x 27.4 (1.08) x 89.3 (3.52)



Redundant CPUs

These CPUs take the process control capabilities of the Q Series process CPUs and add full hot-backup capability by using dual redundant CPUs. Use this system in applications where downtime cannot be tolerated for reasons of safety, equipment damage, financial loss, interruption of service, or regulatory compliance.

Features Include:

  • Prevent controller downtime with dual redundant CPUs (control and back-up). Any failure of the control CPU causes immediate transfer of control to the back-up, preventing system failure or interruption.
  • Synchronize up to 100,000 words of process data between CPUs per scan
  • Switchover time typically around 40ms, insuring “bumpless” transfer
  • CPUs reside on physically separate racks, allowing control CPU to be replaced while back-up maintains system operation
  • Low cost of ownership; most parts are interchangeable with standard Q Series systems
  • Redundant power supply option
  • Redundant MELSECNET/H control level network provides link to I/O stations at up to 25Mbit/s
  • Over 50 process control related instructions (same as Q Process CPUs)
  • Most I/O may be hot swapped

 

Required Manuals
Use same manual set as shown for Q Series Process CPUs, plus the manual listed below.

Model Number

Description

Contents

Included?

Stocked Item

SH(NA)080486ENG

QnPRHCPU User’s Manual
(Redundant System)

Overview • System Configuration • Tracking cable Procedure for starting up a redundant system • Redundant system functions • Redundant system networks • Programming cautions • Troubleshooting Processing time for redundant systems

No (purchase separately)

S

 

Specifications

Model Number

Q12PRHCPU

Q25PRHCPU

Stocked Item

S

S

Control System

Cyclic program scan

I/O Control

Refresh mode

Programming
Language

Sequence Control Dedicated Language

Ladder, list, ST, SFC

Process Control Language

FBD for process control (*1)

Number Of I/O Device Points (*2)

8192 points

Number Of I/O Points (*3)

4096 points

Number Of CPUs Mounted

1 (multiple-CPU configuration is not available)

Number Of Mountable Modules

11 on the main base unit (7 when the power supply is redundant type)

Number Of Extension Base

0 (All non-redundant modules are mounted on the remote I/O station (the maximum number of modules that can be mounted on a remote station is 64).)

Number Of Remote I/O Points

8192 points (up to 2048 points per station)

Program Capacity

Number of Steps

124 ksteps

252 ksteps

Number of Programs

124

252 (*4)

Device Memory Capacity (*5)

Device memory: 29 kwords File register (internal): 128 kwords (Extended up to 1017 kwords by adding a memory card (2 MB))

Instruction Types

Sequence basic/applied instructions, instrumentation instructions Instrumentation instruction types: Control/Operation instructions, I/O control instructions, compensation operation instructions, arithmetic operation instructions, comparison operation instructions, automatic tuning instructions

Functions Compatible with Redundant System

Redundant configuration of the entire system, including the CPU, the power supply, and the base unitHot standby system for the control and standby systems online module change both backup and separate mode available. Large-capacity data tracking: Large-capacity device data transfer (100 kwords) from the control system to the standby system Network system compatible with redundant system: Switchover in case of MELSECNET/H or Ethernet module malfunction or network wire disconnection Engineering environment (GX Developer)

Communication with programming tools: The control system or standby system can be designated by direct connection to the CPU or connection via a network. Online program change function: PLC write, online program change, online multi-block change

Program memory copy function Copying control system: programs to the standby system Redundant system setting: The tracking device and network paring can be set with parameters.

Loop Control Specs.

Control Cycle

10 ms -/control loop (Can be set for each loop.)

Number of Control Loops

No limit (*6)

Main Functions

2-degree-of-freedom PID control, cascade control, automatic tuning function, feed forward control

RAS

Online Module Replacement

The I/O, analog, temperature input, temperature control, and pulse input modules can be replaced (on a remote I/O station).

Output In Case Of Error Stop

Clear or output retention can be designated for each module.

Communication Port

USB, RS-232

Modules That Can Be Mounted On Main Base Unit

Network modules for the Q series can be mounted (Ethernet, MELSECNET/H, and CC-Link only)

Programming Software

GX Developer, PX Developer


Notes:

1. PX Developer is required for programming by FBD.
2. Total number of the I/O points on the main base unit, which are directly controlled from the CPU module, and the I/O points controlled as remote I/O by the remote I/O network.
3. The number of I/O points on the main base unit, which are directly controlled from the CPU module.
4. The max. number of files that can be executed is 124. It is impossible to execute 125 or more files. Two SFC/MELSAP-Ls are available, one of which is a program execution control SFC.
5. Each number of device points in the data memory can be changed within 29 kwords, depending on the parameters.
6. The number of control loops is restricted by the combination of the device memory capacity (128 kwords/loop used) and the control cycle.

 

Q Redundant CPU Parts

Product Name

Model

Overview

Stocked Item

Redundant CPU Module

Q12PRHCPU

Number of I/O points: 8192 (actual number of I/O points: 4096), program capacity: 124 ksteps

S

Q25PRHCPU

Number of I/O points: 8192 (actual number of I/O points: 4096), program capacity: 252 ksteps

S

Tracking Cable

QC10TR

1m cable for tracking

S

QC30TR

3m cable for tracking

S

Base Unit For Redundant

Q38RB-E

Q series I/O mounting main base: Number of power supply slots: 2, number of CPU slots: 1, number of I/O slots: 8

S

Power Supply Systems

Q68RB

Q series I/O mounting extension base: Number of power supply slots: 2, number of I/O slots: 8

S

Power Supply Module For Redundant Power Supply Systems

Q64RP

100 to 120/200 to 240 V AC input, 5 V DC, 8.5 A output

S


 

Communication and Networking Module Version Information For Compatibility With Redundant Systems

Product name

Model

Overview

Version

Stocked Item

MELSECNET/H Master Module

QJ71LP21-25

For MELSECNET/H dual optical loop interface module (compatible with SI and QSI) control / normal / master stations

Function version “D” or later

S

QJ71LP21S-25

For MELSECNET/H dual optical loop interface module (compatible with SI and QSI) control / normal / master stations, equipped with an external power supply

QJ71LP21GE

For MELSECNET/H dual optical loop interface module (compatible with GI) control / normal / master stations

S

QJ71BR11

For MELSECNET/H coaxial single bus interface module control / normal / master stations

S

MELSECNET/H Remote I/O Module

QJ72LP25-25

For MELSECNET/H dual optical loop interface module (compatible with SI and QSI) remote I/O stations (*1)

S

QJ72LP25GE

For MELSECNET/H dual optical loop interface module (compatible with GI) remote I/O stations

S

QJ72BR15

For MELSECNET/H coaxial single bus interface module remote I/O stations

S

Ethernet Interface Module

QJ71E71-B2

Ethernet interface module (10BASE2)

S

QJ71E71-B5

Ethernet interface module (10BASE5)

S

QJ71E71-100

Ethernet interface module (100BASE-TX/10BASE-T)

S

MELSECNET / H Board For Personal Computers

Q80BD-J71LP21-25

For dual optical loop interface board (compatible with SI and QSI) control / normal stations (*1)

S

Q80BD-J71LP21G

For dual optical loop interface board (compatible with GI) control / normal stations (*1)

S

Q80BD-J71BR11

For coaxial single bus interface board control / normal stations (*1)

S

Note:
1. The boards must be used in combination with the attached driver package SW0DNC-MNETH-B[90K] or later version.

 

Q PC CPU

The Q Series is unique in the way it offers the ability to integrate true open control capabilities with conventional automation technologies by way of a PC CPU. This CPU fits directly onto the Q Series base rack and offers complete PC capabilities. The PC CPU may be used either on its own, combined with a sequence CPU, or in a system that combines sequence, motion, process and PC CPUs together. 

Key Features:

  • Available with a choice of hardware configurations        
  • Run conventional Microsoft® Windows® applications, as with any other PC        
  • Combine control of automation via sequence or motion CPUs with third party software applications
  • Full integration with Q Series I/O, special function and networking/communication modules        
  • Offers unlimited application flexibility. Some examples include:        
    • Create custom control systems using third party programming  languages such as Microsoft® Visual Basic®, C++, or other  established languages        
    • Adding multimedia capabilities to systems for operator diagnostics        
    • Adding common business applications for data manipulation and logging to aid quality assurance


Model

PPC-CPU686(MS)-128

Stocked Item

Certification

UL • cUL • CE

CPU

Mobile Celeron Processor-LP 400MHz, FSB100MHz (Intel)

Chipset

440BX (Intel)

Memory

L1 Cache

16KB

L2 Cache

128KB

Main Memory

128MB

Video

Controller

B69000 (C&T)

Video RAM

2 MB (Built in the controller)

CRT I/F

Analog RGB 15-pin HD-SUB connector

Specifications

 

SVGA (800×600)

XGA (1024×768)

Horizontal sync signal frequency

37.9kHz

48.4kHz

Vertical sync signal frequency

60Hz

60Hz

Display colors

16,777,215

65,536

FDD I/F

26-pin half-pitch connector. Optional FDD: PC-FDD25BH

IDE I/F

Primary

40-pin half-pitch connector (Up to 2 units acceptable)

Secondary

Not supported

Serial Interfaces

RS-232C compliant: 2 channels (9-pin D-SUB connector and extension interface (EX.I/F)) Transfer rate: 50 to 115,200 bps

Parallel Interface

1 channel (Extension interface (EX.I/F)). Supported modes: Normal, SPP, EPP 1.7/1.9, ECP

LAN

I/F

Ethernet 100BASE-TX/10BASE-T RJ-45 connector

Controller

82559 (Intel)

PC Cards

Controller

PCI1420 (TI)

Card Type

PCMCIA, CARD-BUS (*1)

Card Slot

Type I/II x 2, or Type III x 1

Display (*2)

Card detection LED (green) x 2

ATA Card Boot (*3)

Enabled only in SLOT 1. Hot plugging not supported as ATA cards are handled as IDE devices

USB I/F (*1)

2 channels (one of which is in the extension interface (EX.I/F)) Ver 1.1 compliant. Transfer rate: 1.5/12 Mbps

Keyboard/PS2 Mouse Interface

6-pin MINI DIN connector (shared by keyboard and mouse).
Both can be used at the same time with a keyboard/mouse
type splitter cable adapter

Watchdog Timers

2 channels
Time-out period: System WDT: 20 msec to 2 sec.
User WDT: 20 msec to 10 sec

RTC/CMOS

Lithium-ion battery backup. Battery life: 10 years min. (at 25°C). Clock precision: [±]1 minute/month (at 25°C)

Display LEDs

RDY (Green), B.RUN (Green), ERR. (Red), USER (Red), BAT. (Orange), EXIT (Green)

Controls

Reset pushbutton, 6-bit DIP switch, 3-position toggle switch

OS’s Supported

Windows 2000 Professional, Windows NT Workstation 4.0, Windows NT Embedded 4.0

Base Unit Slots Occupied

2 slots

Dimensions (W x H x D) mm (in)

55.2 (2.2) x 98.0 (3.9) x 115.0 (4.5) (Excluding protrusions)

Power Consumption (+5 VDC)

5V 3.0A (Max.) (*4)

Acceptable Momentary Power Failure Time

Depends on the power supply module

Weight

470g


Notes:
PC CPU must be ordered as a package. Please refer to the “Q PC CPU Ordering Information” for part numbers.
1. Supported only by Windows 2000.
2. Comes on when the card is recognized normally and remains on until unplugging the card is detected.
3. Handled as drive C when booted from the ATA card. (Otherwise, handling depends on the OS and driver specifications.) Only the OS which can be booted from the ATA card is Windows NT Workstation 4.0 or Windows NT Embedded 4.0. Windows 2000 Professional cannot be booted that way.
4. This does not include the current consumption by any peripheral device (such as the PC Card, USB device, keyboard, or mouse) or by the connector terminal.
5.All trademarks are the property of their owners and acknowledged.

 

Q PC System Configuration

 

Notes:
1. Q PC module must be fitted on right hand side of other CPUs already installed
2. The Q PC occupies a minimum of three physical slots:
PC CPU, 2 slots
Hard disk/silicon disk unit, 1 slot
If additional disk units are being used, these occupy one slot each
3. PPC-COT-01 is an interface which allows the USB, serial and parallel ports available in the expansion port to be accessed individually.



Q Series • Q PC CPU Ordering Information

Q PC CPU Packages

Model No.

Stocked Item

Configuration

PC CPU Unit

Storage Unit + OS

Bus Interface Driver

Recovery CD

PPC-852-21B

PPC-852

PPC-HDD(MS)A

PPC-DRV-01

Windows2000 Professional

PPC-852-21G

 

PPC-HDD(MS)A

Windows XP Professinal

PPC-SET-22F

 

CF-1GB-R

WindowsXP Embedded


Note: “WinNTe” is Windows NT Embedded. All trademarks are the property of their owners and acknowledged.

 

Optional Accessories

Model No.

Stocked Item

Product Name/Description

PPC-HDD(MS)

Hard Disk Unit, 20GB

CF-1GB-R

CF Card, 1GB, (Fixed Disk specification)

IPC-CDD-02

CD-ROM / DVD-ROM Drive (bundled with cable, 40cm) *1

PPC-CDC-01

Connection cable for above

PPC-COT-01

Connector Terminal (bundled with cable, 1m)

PPC-SSC-01

Serial Conversion Cable, 36-pin half pitch to 9-pin D-SUB, 50cm in cable length

PPC-HBR-01

Hard Disk Unit, shock proof fixing bracket
PPC-DINAD-01

Adaptor to install PPC-COT-01 on DIN Rail

PPC-CPU852(MS)-MU

English version of the User’s Manual Set) PC CPU Unit + Bus Interface Driver)


Notes:
1.When connecting with a PC CPU Unit and installing OS in CF card, bundle cable cannot be used.
2. When OS is installed in CF Card pf PC CPU main part, it is required for connection with IPC-CDD-02.

 

 Table
of Contents